Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
There is a constant need to shrink the size of the memory cell arrays in order to maximize the number of memory cells on a single wafer. It is well known that forming memory cells in pairs, with each pair sharing a single source region, and with adjacent pairs of cells sharing a common drain region, reduces the size of the memory cell array. However, a large area of the array is typically reserved for the bit-line connection to the drain regions. The bit-line area is often occupied by the contact openings between memory cell pairs, and the contact to wordline spacing (which strongly depends upon lithography generation), contact alignment and contact integrity. In addition, significant space is reserved for the word-line transistor, the size of which is set by lithography generation and junction scaling.
Another aspect addressed by the present invention involves the erase performance of the memory cell. FIG. 1 illustrates a well known non-volatile memory cell design, which includes a floating gate 1 disposed over and insulated from a semiconductor substrate 2 having source and drain regions 3/4. A control gate 5 has a first portion that is disposed laterally adjacent to the floating gate 1, and a second portion that is disposed vertically over and overlapping the floating gate 1. The floating gate 1 includes a relatively sharp edge 6 that extends upwardly toward the control gate second portion. The edge 6 extending toward the overlapping portion of the control gate 5 enhances Fowler-Nordheim tunneling used to erase the memory cell. As the cell size is scaled down, at least some of the overlap between control gate 5 and floating gate 1 must be maintained so that the upwardly oriented pointed edges can be used for the erase function. This cell architecture imposes a scaling limit on the erase coupling ratio due to the finite overlap capacitance between the control gate 5 and the floating gate 1.
There is a need for a non-volatile, floating gate type memory cell array with significant cell size reduction without adversely compromising the erase coupling ratio of the memory cell.